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<a href="#nested-classes">Data Structures</a> &#124;
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_mipi___tx___phy___config.html">XMipi_Tx_Phy_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The configuration structure for mipi_tx_phy.  <a href="struct_x_mipi___tx___phy___config.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Xmipi_tx_phy Controller driver instance data.  <a href="struct_x_mipi___tx___phy.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Macros</h2></td></tr>
<tr class="memitem:gafab4174d7ffe2e9118d2f388914f26e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gafab4174d7ffe2e9118d2f388914f26e3">XMIPI_TX_PHY_H_</a></td></tr>
<tr class="memdesc:gafab4174d7ffe2e9118d2f388914f26e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#gafab4174d7ffe2e9118d2f388914f26e3">More...</a><br/></td></tr>
<tr class="separator:gafab4174d7ffe2e9118d2f388914f26e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6bd9c3f2f20cf79b7bd8a52a67b36467"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga6bd9c3f2f20cf79b7bd8a52a67b36467">XMIPI_TX_PHY_HW_H_</a></td></tr>
<tr class="memdesc:ga6bd9c3f2f20cf79b7bd8a52a67b36467"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#ga6bd9c3f2f20cf79b7bd8a52a67b36467">More...</a><br/></td></tr>
<tr class="separator:ga6bd9c3f2f20cf79b7bd8a52a67b36467"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga6e9c7bebd5db9ead39815cac90867d2f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga6e9c7bebd5db9ead39815cac90867d2f">XMipi_Tx_Phy_CfgInitialize</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr, <a class="el" href="struct_x_mipi___tx___phy___config.html">XMipi_Tx_Phy_Config</a> *CfgPtr, UINTPTR EffectiveAddr)</td></tr>
<tr class="memdesc:ga6e9c7bebd5db9ead39815cac90867d2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance provided by the caller based on the given Config structure.  <a href="#ga6e9c7bebd5db9ead39815cac90867d2f">More...</a><br/></td></tr>
<tr class="separator:ga6e9c7bebd5db9ead39815cac90867d2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0edf3de0af6e081ab9ec6ba03bcb029d"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr, u8 Handle, u32 Value)</td></tr>
<tr class="memdesc:ga0edf3de0af6e081ab9ec6ba03bcb029d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the registers of the Mipi_Tx_Phy instance.  <a href="#ga0edf3de0af6e081ab9ec6ba03bcb029d">More...</a><br/></td></tr>
<tr class="separator:ga0edf3de0af6e081ab9ec6ba03bcb029d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad55317d23f56c8dd601c6970d5d6228e"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gad55317d23f56c8dd601c6970d5d6228e">XMipi_Tx_Phy_GetRegIntfcPresent</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr)</td></tr>
<tr class="memdesc:gad55317d23f56c8dd601c6970d5d6228e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get if register interface is present from the config structure for specified Mipi_Tx_Phy instance.  <a href="#gad55317d23f56c8dd601c6970d5d6228e">More...</a><br/></td></tr>
<tr class="separator:gad55317d23f56c8dd601c6970d5d6228e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3647fa8d8f8ed5ef13a940a00959ce90"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr, u8 Handle)</td></tr>
<tr class="memdesc:ga3647fa8d8f8ed5ef13a940a00959ce90"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get information stored in the Mipi_Tx_Phy instance based on the handle passed.  <a href="#ga3647fa8d8f8ed5ef13a940a00959ce90">More...</a><br/></td></tr>
<tr class="separator:ga3647fa8d8f8ed5ef13a940a00959ce90"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60dbd7f0c7cc211f6ed1e97c8c1dd8c0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga60dbd7f0c7cc211f6ed1e97c8c1dd8c0">XMipi_Tx_Phy_Reset</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga60dbd7f0c7cc211f6ed1e97c8c1dd8c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to do a soft reset of the Mipi_Tx_Phy IP instance.  <a href="#ga60dbd7f0c7cc211f6ed1e97c8c1dd8c0">More...</a><br/></td></tr>
<tr class="separator:ga60dbd7f0c7cc211f6ed1e97c8c1dd8c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0e324919c833e8a3044f5807a4e88a6f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga0e324919c833e8a3044f5807a4e88a6f">XMipi_Tx_Phy_ClearDataLane</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr, u8 DataLane, u32 Mask)</td></tr>
<tr class="memdesc:ga0e324919c833e8a3044f5807a4e88a6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to clear the Abort Error (Escape or High Speed) bits in the Data Lane 0 through 3.  <a href="#ga0e324919c833e8a3044f5807a4e88a6f">More...</a><br/></td></tr>
<tr class="separator:ga0e324919c833e8a3044f5807a4e88a6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96324c0e81aae087966b15ed5478830e"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga96324c0e81aae087966b15ed5478830e">XMipi_Tx_Phy_GetClkLaneStatus</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga96324c0e81aae087966b15ed5478830e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get information about Clock Lane status.  <a href="#ga96324c0e81aae087966b15ed5478830e">More...</a><br/></td></tr>
<tr class="separator:ga96324c0e81aae087966b15ed5478830e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa1ad1388f716aaff8073d17268341007"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaa1ad1388f716aaff8073d17268341007">XMipi_Tx_Phy_GetClkLaneMode</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaa1ad1388f716aaff8073d17268341007"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get specific Lane mode information about Clock Lane.  <a href="#gaa1ad1388f716aaff8073d17268341007">More...</a><br/></td></tr>
<tr class="separator:gaa1ad1388f716aaff8073d17268341007"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga30186d35cb2a9a6e8c176a2e12b8fc3c"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga30186d35cb2a9a6e8c176a2e12b8fc3c">XMipi_Tx_Phy_GetDataLaneStatus</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr, u8 DataLane)</td></tr>
<tr class="memdesc:ga30186d35cb2a9a6e8c176a2e12b8fc3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get information about a Data Lane status.  <a href="#ga30186d35cb2a9a6e8c176a2e12b8fc3c">More...</a><br/></td></tr>
<tr class="separator:ga30186d35cb2a9a6e8c176a2e12b8fc3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9e0be75428b66fe7d9f22b8b223e66b"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaf9e0be75428b66fe7d9f22b8b223e66b">XMipi_Tx_Phy_GetDLCalibStatus</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr, u8 DataLane)</td></tr>
<tr class="memdesc:gaf9e0be75428b66fe7d9f22b8b223e66b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get Data Lane Calibration status.  <a href="#gaf9e0be75428b66fe7d9f22b8b223e66b">More...</a><br/></td></tr>
<tr class="separator:gaf9e0be75428b66fe7d9f22b8b223e66b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga921e82addba856d2b57c15ac8ace54eb"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga921e82addba856d2b57c15ac8ace54eb">XMipi_Tx_Phy_GetDataLaneMode</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr, u8 DataLane)</td></tr>
<tr class="memdesc:ga921e82addba856d2b57c15ac8ace54eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get specfic Lane mode information about a Data Lane.  <a href="#ga921e82addba856d2b57c15ac8ace54eb">More...</a><br/></td></tr>
<tr class="separator:ga921e82addba856d2b57c15ac8ace54eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae03f90199460c27b38aca1a9eecd973c"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gae03f90199460c27b38aca1a9eecd973c">XMipi_Tx_Phy_GetPacketCount</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr, u8 DataLane)</td></tr>
<tr class="memdesc:gae03f90199460c27b38aca1a9eecd973c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get count of packets received on each lane.  <a href="#gae03f90199460c27b38aca1a9eecd973c">More...</a><br/></td></tr>
<tr class="separator:gae03f90199460c27b38aca1a9eecd973c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga35253890ab16b4233209c20890d18ecb"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga35253890ab16b4233209c20890d18ecb">XMipi_Tx_Phy_GetVersionReg</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga35253890ab16b4233209c20890d18ecb"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is used to get Mipi_Tx_Phy Version.  <a href="#ga35253890ab16b4233209c20890d18ecb">More...</a><br/></td></tr>
<tr class="separator:ga35253890ab16b4233209c20890d18ecb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ea4f73d453197f5d121170ae4db05c9"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga1ea4f73d453197f5d121170ae4db05c9">XMipi_Tx_Phy_Activate</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr, u8 Flag)</td></tr>
<tr class="memdesc:ga1ea4f73d453197f5d121170ae4db05c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used to enable or disable the Mipi_Tx_Phy core.  <a href="#ga1ea4f73d453197f5d121170ae4db05c9">More...</a><br/></td></tr>
<tr class="separator:ga1ea4f73d453197f5d121170ae4db05c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6aca7437c8f5880a23d50fa3e8c3ef98"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_mipi___tx___phy___config.html">XMipi_Tx_Phy_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga6aca7437c8f5880a23d50fa3e8c3ef98">XMipi_Tx_Phy_LookupConfig</a> (UINTPTR BaseAddress)</td></tr>
<tr class="memdesc:ga6aca7437c8f5880a23d50fa3e8c3ef98"><td class="mdescLeft">&#160;</td><td class="mdescRight">Look up the hardware configuration for a device instance.  <a href="#ga6aca7437c8f5880a23d50fa3e8c3ef98">More...</a><br/></td></tr>
<tr class="separator:ga6aca7437c8f5880a23d50fa3e8c3ef98"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a6f46a83ce56b8538bd115feb1e652f"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga4a6f46a83ce56b8538bd115feb1e652f">XMipi_Tx_Phy_SelfTest</a> (<a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga4a6f46a83ce56b8538bd115feb1e652f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Runs a self-test on the driver/device.  <a href="#ga4a6f46a83ce56b8538bd115feb1e652f">More...</a><br/></td></tr>
<tr class="separator:ga4a6f46a83ce56b8538bd115feb1e652f"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
mipi_tx_phy Modes</h2></td></tr>
<tr class="memitem:ga684f9034514d9b4d41fd459c14b7bc7d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga684f9034514d9b4d41fd459c14b7bc7d">XMIPI_TX_PHY_MODE_MIN</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga684f9034514d9b4d41fd459c14b7bc7d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lower limit for Mode.  <a href="#ga684f9034514d9b4d41fd459c14b7bc7d">More...</a><br/></td></tr>
<tr class="separator:ga684f9034514d9b4d41fd459c14b7bc7d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb09e64b9efe4ca20303e3ed180d6659"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gafb09e64b9efe4ca20303e3ed180d6659">XMIPI_TX_PHY_LOW_POWER_MODE</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gafb09e64b9efe4ca20303e3ed180d6659"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane in Low Power Mode.  <a href="#gafb09e64b9efe4ca20303e3ed180d6659">More...</a><br/></td></tr>
<tr class="separator:gafb09e64b9efe4ca20303e3ed180d6659"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc5e0ad6781683237fd31b86e224674d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gabc5e0ad6781683237fd31b86e224674d">XMIPI_TX_PHY_HIGH_POWER_MODE</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gabc5e0ad6781683237fd31b86e224674d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane in High Power Mode.  <a href="#gabc5e0ad6781683237fd31b86e224674d">More...</a><br/></td></tr>
<tr class="separator:gabc5e0ad6781683237fd31b86e224674d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9e75abdbbf8a802143da1077354cf90c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga9e75abdbbf8a802143da1077354cf90c">XMIPI_TX_PHY_ESCAPE_MODE</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga9e75abdbbf8a802143da1077354cf90c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane in Escape Mode.  <a href="#ga9e75abdbbf8a802143da1077354cf90c">More...</a><br/></td></tr>
<tr class="separator:ga9e75abdbbf8a802143da1077354cf90c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d59eea69940bc10dc100faa0983bc55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga1d59eea69940bc10dc100faa0983bc55">XMIPI_TX_PHY_MODE_MAX</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga1d59eea69940bc10dc100faa0983bc55"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper Limit for mode.  <a href="#ga1d59eea69940bc10dc100faa0983bc55">More...</a><br/></td></tr>
<tr class="separator:ga1d59eea69940bc10dc100faa0983bc55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ef76131f9278a362a29e94fda961943"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga9ef76131f9278a362a29e94fda961943">XMIPI_TX_PHY_MAX_LANES_V10</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga9ef76131f9278a362a29e94fda961943"><td class="mdescLeft">&#160;</td><td class="mdescRight">V1.0 supports 4 Lanes.  <a href="#ga9ef76131f9278a362a29e94fda961943">More...</a><br/></td></tr>
<tr class="separator:ga9ef76131f9278a362a29e94fda961943"><td class="memSeparator" colspan="2">&#160;</td></tr>
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mipi_tx_phy Info Handles</h2></td></tr>
<tr class="memitem:ga0ecee03940210ec82dde89faefb8f456"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga0ecee03940210ec82dde89faefb8f456">XMIPI_TX_PHY_HANDLE_MIN</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga0ecee03940210ec82dde89faefb8f456"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lower Bound for XMIPI_TX_PHY_HANDLE.  <a href="#ga0ecee03940210ec82dde89faefb8f456">More...</a><br/></td></tr>
<tr class="separator:ga0ecee03940210ec82dde89faefb8f456"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga794d4197e4f32ea40dc8010b2ae0185c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga794d4197e4f32ea40dc8010b2ae0185c">XMIPI_TX_PHY_HANDLE_INIT_TIMER</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga794d4197e4f32ea40dc8010b2ae0185c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Initialization Timer.  <a href="#ga794d4197e4f32ea40dc8010b2ae0185c">More...</a><br/></td></tr>
<tr class="separator:ga794d4197e4f32ea40dc8010b2ae0185c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga45d5dd17088900a16fec2d4ec72055fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga45d5dd17088900a16fec2d4ec72055fb">XMIPI_TX_PHY_HANDLE_HSTIMEOUT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga45d5dd17088900a16fec2d4ec72055fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for HS Timeout.  <a href="#ga45d5dd17088900a16fec2d4ec72055fb">More...</a><br/></td></tr>
<tr class="separator:ga45d5dd17088900a16fec2d4ec72055fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf48cd41ce4fbada5662e23018611c003"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaf48cd41ce4fbada5662e23018611c003">XMIPI_TX_PHY_HANDLE_ESCTIMEOUT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gaf48cd41ce4fbada5662e23018611c003"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Escape Timeout.  <a href="#gaf48cd41ce4fbada5662e23018611c003">More...</a><br/></td></tr>
<tr class="separator:gaf48cd41ce4fbada5662e23018611c003"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2792b35f19f06efb8b6adb0c3e7c0f7f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga2792b35f19f06efb8b6adb0c3e7c0f7f">XMIPI_TX_PHY_HANDLE_CLKLANE</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga2792b35f19f06efb8b6adb0c3e7c0f7f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Clock Lane.  <a href="#ga2792b35f19f06efb8b6adb0c3e7c0f7f">More...</a><br/></td></tr>
<tr class="separator:ga2792b35f19f06efb8b6adb0c3e7c0f7f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ca0ab2cf3f6b368c2454200b780ef03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga8ca0ab2cf3f6b368c2454200b780ef03">XMIPI_TX_PHY_HANDLE_DLANE0</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:ga8ca0ab2cf3f6b368c2454200b780ef03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Data Lane 0.  <a href="#ga8ca0ab2cf3f6b368c2454200b780ef03">More...</a><br/></td></tr>
<tr class="separator:ga8ca0ab2cf3f6b368c2454200b780ef03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8fa083c47f619744ed568fcc76d1d4aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga8fa083c47f619744ed568fcc76d1d4aa">XMIPI_TX_PHY_HANDLE_DLANE1</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga8fa083c47f619744ed568fcc76d1d4aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Data Lane 1.  <a href="#ga8fa083c47f619744ed568fcc76d1d4aa">More...</a><br/></td></tr>
<tr class="separator:ga8fa083c47f619744ed568fcc76d1d4aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ebd16502a0c0ee0d4b0cb99c7b4af94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga7ebd16502a0c0ee0d4b0cb99c7b4af94">XMIPI_TX_PHY_HANDLE_DLANE2</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:ga7ebd16502a0c0ee0d4b0cb99c7b4af94"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Data Lane 2.  <a href="#ga7ebd16502a0c0ee0d4b0cb99c7b4af94">More...</a><br/></td></tr>
<tr class="separator:ga7ebd16502a0c0ee0d4b0cb99c7b4af94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga61d3f8f2a197488723c7f18de5fa4452"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga61d3f8f2a197488723c7f18de5fa4452">XMIPI_TX_PHY_HANDLE_DLANE3</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga61d3f8f2a197488723c7f18de5fa4452"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handle for Data Lane 3.  <a href="#ga61d3f8f2a197488723c7f18de5fa4452">More...</a><br/></td></tr>
<tr class="separator:ga61d3f8f2a197488723c7f18de5fa4452"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4dd60256bbac14dbc8b023397aa7a4ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga4dd60256bbac14dbc8b023397aa7a4ef">XMIPI_TX_PHY_HANDLE_MAX</a>&#160;&#160;&#160;9</td></tr>
<tr class="memdesc:ga4dd60256bbac14dbc8b023397aa7a4ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper Bound for XMIPI_TX_PHY_HANDLE.  <a href="#ga4dd60256bbac14dbc8b023397aa7a4ef">More...</a><br/></td></tr>
<tr class="separator:ga4dd60256bbac14dbc8b023397aa7a4ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
mipi_tx_phy HSTIMEOUT range</h2></td></tr>
<tr class="memitem:gaaf2e6f503d4b86cf6d1c9833fcaea04b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaaf2e6f503d4b86cf6d1c9833fcaea04b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_TX_PHY_HS_TIMEOUT_MIN_VALUE</b>&#160;&#160;&#160;10000UL</td></tr>
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<tr class="memitem:ga9f5d073f4808e8cba74268dd3c07e994"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9f5d073f4808e8cba74268dd3c07e994"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_TX_PHY_HS_TIMEOUT_MAX_VALUE</b>&#160;&#160;&#160;65541UL</td></tr>
<tr class="separator:ga9f5d073f4808e8cba74268dd3c07e994"><td class="memSeparator" colspan="2">&#160;</td></tr>
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mipi_tx_phy HSSETTLE range</h2></td></tr>
<tr class="memitem:gaf5b568320116f8e0335eaa22f7faeb0b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf5b568320116f8e0335eaa22f7faeb0b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_TX_PHY_HS_SETTLE_MAX_VALUE</b>&#160;&#160;&#160;0x1FF</td></tr>
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mipi_tx_phy Flags to Enable or Disable core</h2></td></tr>
<tr class="memitem:gaafd73ecc355cb1283c3feaad86e6e66b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaafd73ecc355cb1283c3feaad86e6e66b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_TX_PHY_ENABLE_FLAG</b>&#160;&#160;&#160;1</td></tr>
<tr class="separator:gaafd73ecc355cb1283c3feaad86e6e66b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga81f9f63f8833a3f98ffac4354b419046"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga81f9f63f8833a3f98ffac4354b419046"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_TX_PHY_DISABLE_FLAG</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:ga81f9f63f8833a3f98ffac4354b419046"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Device registers</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe905567f3f1e4630e21d2f8192509576"></a>Register sets of MIPI_TX_PHY </p>
</td></tr>
<tr class="memitem:gabbf8c59ccf6c1abcef8dd1c7cb06473c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gabbf8c59ccf6c1abcef8dd1c7cb06473c">XMIPI_TX_PHY_CTRL_REG_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:gabbf8c59ccf6c1abcef8dd1c7cb06473c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register.  <a href="#gabbf8c59ccf6c1abcef8dd1c7cb06473c">More...</a><br/></td></tr>
<tr class="separator:gabbf8c59ccf6c1abcef8dd1c7cb06473c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e16ded337e70f28b3ba7c3c791f736a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga6e16ded337e70f28b3ba7c3c791f736a">XMIPI_TX_PHY_VERSION_REG_OFFSET</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga6e16ded337e70f28b3ba7c3c791f736a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Version Register.  <a href="#ga6e16ded337e70f28b3ba7c3c791f736a">More...</a><br/></td></tr>
<tr class="separator:ga6e16ded337e70f28b3ba7c3c791f736a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga06d4f400a133fadb577204eb236d8b60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga06d4f400a133fadb577204eb236d8b60">XMIPI_TX_PHY_INIT_TIMER_REG_OFFSET</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga06d4f400a133fadb577204eb236d8b60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialization Timer Register.  <a href="#ga06d4f400a133fadb577204eb236d8b60">More...</a><br/></td></tr>
<tr class="separator:ga06d4f400a133fadb577204eb236d8b60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga38135baf5eb6b624dacae2760a87f276"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga38135baf5eb6b624dacae2760a87f276">XMIPI_TX_PHY_HSTIMEOUT_REG_OFFSET</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga38135baf5eb6b624dacae2760a87f276"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog timeout in HS mode Register.  <a href="#ga38135baf5eb6b624dacae2760a87f276">More...</a><br/></td></tr>
<tr class="separator:ga38135baf5eb6b624dacae2760a87f276"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3dd41b223fba7f1f0c099f9444944b19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga3dd41b223fba7f1f0c099f9444944b19">XMIPI_TX_PHY_ESCTIMEOUT_REG_OFFSET</a>&#160;&#160;&#160;0x00000014</td></tr>
<tr class="memdesc:ga3dd41b223fba7f1f0c099f9444944b19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Goto Stop state on timeout timer Register.  <a href="#ga3dd41b223fba7f1f0c099f9444944b19">More...</a><br/></td></tr>
<tr class="separator:ga3dd41b223fba7f1f0c099f9444944b19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee3555d2cc9dc91c2f13f39f246af4ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaee3555d2cc9dc91c2f13f39f246af4ac">XMIPI_TX_PHY_CLSTATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000018</td></tr>
<tr class="memdesc:gaee3555d2cc9dc91c2f13f39f246af4ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clk lane PHY error Status Register.  <a href="#gaee3555d2cc9dc91c2f13f39f246af4ac">More...</a><br/></td></tr>
<tr class="separator:gaee3555d2cc9dc91c2f13f39f246af4ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga77c981eb784b931ddee9637d03dfafa6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga77c981eb784b931ddee9637d03dfafa6">XMIPI_TX_PHY_DL0STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x0000001C</td></tr>
<tr class="memdesc:ga77c981eb784b931ddee9637d03dfafa6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 0 PHY error Status Register.  <a href="#ga77c981eb784b931ddee9637d03dfafa6">More...</a><br/></td></tr>
<tr class="separator:ga77c981eb784b931ddee9637d03dfafa6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16d4d03a4897453d51733d12036c3b02"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga16d4d03a4897453d51733d12036c3b02">XMIPI_TX_PHY_DL1STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga16d4d03a4897453d51733d12036c3b02"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 1 PHY error Status Register.  <a href="#ga16d4d03a4897453d51733d12036c3b02">More...</a><br/></td></tr>
<tr class="separator:ga16d4d03a4897453d51733d12036c3b02"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf23b1a894f2241c14d64c555f90a7447"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaf23b1a894f2241c14d64c555f90a7447">XMIPI_TX_PHY_DL2STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000024</td></tr>
<tr class="memdesc:gaf23b1a894f2241c14d64c555f90a7447"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 2 PHY error Status Register.  <a href="#gaf23b1a894f2241c14d64c555f90a7447">More...</a><br/></td></tr>
<tr class="separator:gaf23b1a894f2241c14d64c555f90a7447"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79aad6bfa8e6ae4383887cb10eeb7ef8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga79aad6bfa8e6ae4383887cb10eeb7ef8">XMIPI_TX_PHY_DL3STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000028</td></tr>
<tr class="memdesc:ga79aad6bfa8e6ae4383887cb10eeb7ef8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 3 PHY error Status Register.  <a href="#ga79aad6bfa8e6ae4383887cb10eeb7ef8">More...</a><br/></td></tr>
<tr class="separator:ga79aad6bfa8e6ae4383887cb10eeb7ef8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga595261095922dacb175e9b163bd5f31b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga595261095922dacb175e9b163bd5f31b">XMIPI_TX_PHY_PROG_SEQ_CTRL_OFFSET</a>&#160;&#160;&#160;0x00000038</td></tr>
<tr class="memdesc:ga595261095922dacb175e9b163bd5f31b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prog Seq Control Register.  <a href="#ga595261095922dacb175e9b163bd5f31b">More...</a><br/></td></tr>
<tr class="separator:ga595261095922dacb175e9b163bd5f31b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab4e89fb7aee1d0061973313026d5e6cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gab4e89fb7aee1d0061973313026d5e6cd">XMIPI_TX_PHY_PROG_SEQ_DATA0_OFFSET</a>&#160;&#160;&#160;0x0000003C</td></tr>
<tr class="memdesc:gab4e89fb7aee1d0061973313026d5e6cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prog Seq Data Register 0.  <a href="#gab4e89fb7aee1d0061973313026d5e6cd">More...</a><br/></td></tr>
<tr class="separator:gab4e89fb7aee1d0061973313026d5e6cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7de26ed0365215b08af78324dfb3550b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga7de26ed0365215b08af78324dfb3550b">XMIPI_TX_PHY_PROG_SEQ_DATA1_OFFSET</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga7de26ed0365215b08af78324dfb3550b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prog Seq Data Register 1.  <a href="#ga7de26ed0365215b08af78324dfb3550b">More...</a><br/></td></tr>
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Bitmasks and offsets of XMIPI_TX_PHY_CTRL_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp4d0fcbd2f4e22c61d0fd9bdcbb846d70"></a>This register is used for the enabling/disabling and resetting the MIPI_TX_PHY </p>
</td></tr>
<tr class="memitem:gaff7758fee41117064aa8d27b5ee69de7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaff7758fee41117064aa8d27b5ee69de7">XMIPI_TX_PHY_CTRL_REG_SOFTRESET_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaff7758fee41117064aa8d27b5ee69de7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Soft Reset.  <a href="#gaff7758fee41117064aa8d27b5ee69de7">More...</a><br/></td></tr>
<tr class="separator:gaff7758fee41117064aa8d27b5ee69de7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8340e846c67ddfc75a11bbd4ac5269d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gae8340e846c67ddfc75a11bbd4ac5269d">XMIPI_TX_PHY_CTRL_REG_PHYEN_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gae8340e846c67ddfc75a11bbd4ac5269d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable/Disable controller.  <a href="#gae8340e846c67ddfc75a11bbd4ac5269d">More...</a><br/></td></tr>
<tr class="separator:gae8340e846c67ddfc75a11bbd4ac5269d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab53fbae94c162e2810f2e8bc4d19130"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaab53fbae94c162e2810f2e8bc4d19130">XMIPI_TX_PHY_CTRL_REG_SOFTRESET_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gaab53fbae94c162e2810f2e8bc4d19130"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Soft Reset.  <a href="#gaab53fbae94c162e2810f2e8bc4d19130">More...</a><br/></td></tr>
<tr class="separator:gaab53fbae94c162e2810f2e8bc4d19130"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba9c09bed36f1c618981e53063651f68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaba9c09bed36f1c618981e53063651f68">XMIPI_TX_PHY_CTRL_REG_PHYEN_OFFSET</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gaba9c09bed36f1c618981e53063651f68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for PHY Enable.  <a href="#gaba9c09bed36f1c618981e53063651f68">More...</a><br/></td></tr>
<tr class="separator:gaba9c09bed36f1c618981e53063651f68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1eb36a3a4dac7d8bb40282fc26f16f35"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga1eb36a3a4dac7d8bb40282fc26f16f35">XMIPI_TX_PHY_PROG_SEQ_EN_MASK</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:ga1eb36a3a4dac7d8bb40282fc26f16f35"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable/Disable Prog Seq.  <a href="#ga1eb36a3a4dac7d8bb40282fc26f16f35">More...</a><br/></td></tr>
<tr class="separator:ga1eb36a3a4dac7d8bb40282fc26f16f35"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmasks and offsets of XMIPI_TX_PHY_INIT_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpa763a2701be4706860a56a55ed83c11e"></a>This register is used for lane Initialization.</p>
<p>Recommended to use 1ms or longer in for TX mode and 200us-500us for RX mode </p>
</td></tr>
<tr class="memitem:gaf73370659b96757f31e43b0b82e6cc80"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaf73370659b96757f31e43b0b82e6cc80">XMIPI_TX_PHY_INIT_REG_VAL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:gaf73370659b96757f31e43b0b82e6cc80"><td class="mdescLeft">&#160;</td><td class="mdescRight">Init Timer value in ns.  <a href="#gaf73370659b96757f31e43b0b82e6cc80">More...</a><br/></td></tr>
<tr class="separator:gaf73370659b96757f31e43b0b82e6cc80"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga08167d1c5a8c66e26d2dbf0728f64be6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga08167d1c5a8c66e26d2dbf0728f64be6">XMIPI_TX_PHY_INIT_REG_VAL_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga08167d1c5a8c66e26d2dbf0728f64be6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Init Timer.  <a href="#ga08167d1c5a8c66e26d2dbf0728f64be6">More...</a><br/></td></tr>
<tr class="separator:ga08167d1c5a8c66e26d2dbf0728f64be6"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmask and offset of XMIPI_TX_PHY_HSTIMEOUT_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpf8f73daf102975c86548b61994eff378"></a>This register is used to program watchdog timer in high speed mode.</p>
<p>Default value is 65541. Valid range 1000-65541. </p>
</td></tr>
<tr class="memitem:gad649853612197175df11883ab64abe41"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gad649853612197175df11883ab64abe41">XMIPI_TX_PHY_HSTIMEOUT_REG_TIMEOUT_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:gad649853612197175df11883ab64abe41"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS_TX_TIMEOUT Received.  <a href="#gad649853612197175df11883ab64abe41">More...</a><br/></td></tr>
<tr class="separator:gad649853612197175df11883ab64abe41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga002f9c985356152a355bc1f44b021366"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga002f9c985356152a355bc1f44b021366">XMIPI_TX_PHY_HSTIMEOUT_REG_TIMEOUT_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga002f9c985356152a355bc1f44b021366"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Timeout.  <a href="#ga002f9c985356152a355bc1f44b021366">More...</a><br/></td></tr>
<tr class="separator:ga002f9c985356152a355bc1f44b021366"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmask and offset of XMIPI_TX_PHY_ESCTIMEOUT_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp18885ef91b453f04ce1015599a9e750d"></a>This register contains Rx Data Lanes timeout for watchdog timer in escape mode. </p>
</td></tr>
<tr class="memitem:ga3b3542421ec553cab65cbdb1145b146a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga3b3542421ec553cab65cbdb1145b146a">XMIPI_TX_PHY_ESCTIMEOUT_REG_VAL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga3b3542421ec553cab65cbdb1145b146a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Escape Timout Value.  <a href="#ga3b3542421ec553cab65cbdb1145b146a">More...</a><br/></td></tr>
<tr class="separator:ga3b3542421ec553cab65cbdb1145b146a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1b47a9cfeecf567a00b6ae5e3b1ae55"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaf1b47a9cfeecf567a00b6ae5e3b1ae55">XMIPI_TX_PHY_ESCTIMEOUT_REG_VAL_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gaf1b47a9cfeecf567a00b6ae5e3b1ae55"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Escape Timeout.  <a href="#gaf1b47a9cfeecf567a00b6ae5e3b1ae55">More...</a><br/></td></tr>
<tr class="separator:gaf1b47a9cfeecf567a00b6ae5e3b1ae55"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmask and offset of XMIPI_TX_PHY_CLSTATUS_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp9f23d089f723ff58462cf89a4a274b38"></a>This register contains the clock lane status and state machine control. </p>
</td></tr>
<tr class="memitem:ga89763534a7c4bbbb64696d34d35df25c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga89763534a7c4bbbb64696d34d35df25c">XMIPI_TX_PHY_CLSTATUS_REG_ERRCTRL_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga89763534a7c4bbbb64696d34d35df25c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock lane control error.  <a href="#ga89763534a7c4bbbb64696d34d35df25c">More...</a><br/></td></tr>
<tr class="separator:ga89763534a7c4bbbb64696d34d35df25c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9bcfcbfc2bc59101377b603ee65b87ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga9bcfcbfc2bc59101377b603ee65b87ae">XMIPI_TX_PHY_CLSTATUS_REG_STOPSTATE_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga9bcfcbfc2bc59101377b603ee65b87ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock lane stop state.  <a href="#ga9bcfcbfc2bc59101377b603ee65b87ae">More...</a><br/></td></tr>
<tr class="separator:ga9bcfcbfc2bc59101377b603ee65b87ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2b1c1cac54af04e31c36599ed6e8062a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga2b1c1cac54af04e31c36599ed6e8062a">XMIPI_TX_PHY_CLSTATUS_REG_INITDONE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga2b1c1cac54af04e31c36599ed6e8062a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialization done bit.  <a href="#ga2b1c1cac54af04e31c36599ed6e8062a">More...</a><br/></td></tr>
<tr class="separator:ga2b1c1cac54af04e31c36599ed6e8062a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6aece57daaccf4f982fddf764b15a868"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga6aece57daaccf4f982fddf764b15a868">XMIPI_TX_PHY_CLSTATUS_REG_ULPS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga6aece57daaccf4f982fddf764b15a868"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set in ULPS mode.  <a href="#ga6aece57daaccf4f982fddf764b15a868">More...</a><br/></td></tr>
<tr class="separator:ga6aece57daaccf4f982fddf764b15a868"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaec485fecc0d01a6803f437395cc66f5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaec485fecc0d01a6803f437395cc66f5b">XMIPI_TX_PHY_CLSTATUS_REG_MODE_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:gaec485fecc0d01a6803f437395cc66f5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Low, High, Esc mode.  <a href="#gaec485fecc0d01a6803f437395cc66f5b">More...</a><br/></td></tr>
<tr class="separator:gaec485fecc0d01a6803f437395cc66f5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ec9bd18504fe7f5dacbc1bf777d1924"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0ec9bd18504fe7f5dacbc1bf777d1924"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_TX_PHY_CLSTATUS_ALLMASK</b></td></tr>
<tr class="separator:ga0ec9bd18504fe7f5dacbc1bf777d1924"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga17528c58e673adc82f62fbeab06b22b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga17528c58e673adc82f62fbeab06b22b8">XMIPI_TX_PHY_CLSTATUS_REG_ERRCTRL_OFFSET</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:ga17528c58e673adc82f62fbeab06b22b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Control Error on Clock.  <a href="#ga17528c58e673adc82f62fbeab06b22b8">More...</a><br/></td></tr>
<tr class="separator:ga17528c58e673adc82f62fbeab06b22b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9f13683048291c23c8a62cb99de4159a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga9f13683048291c23c8a62cb99de4159a">XMIPI_TX_PHY_CLSTATUS_REG_STOPSTATE_OFFSET</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga9f13683048291c23c8a62cb99de4159a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Stop State on Clock.  <a href="#ga9f13683048291c23c8a62cb99de4159a">More...</a><br/></td></tr>
<tr class="separator:ga9f13683048291c23c8a62cb99de4159a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace4f962db90a3d55720867e7e0eb81cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gace4f962db90a3d55720867e7e0eb81cc">XMIPI_TX_PHY_CLSTATUS_REG_INITDONE_OFFSET</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gace4f962db90a3d55720867e7e0eb81cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Initialization Done.  <a href="#gace4f962db90a3d55720867e7e0eb81cc">More...</a><br/></td></tr>
<tr class="separator:gace4f962db90a3d55720867e7e0eb81cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3ad7fcdb85bb50e61fccaa519274bd6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga3ad7fcdb85bb50e61fccaa519274bd6f">XMIPI_TX_PHY_CLSTATUS_REG_ULPS_OFFSET</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga3ad7fcdb85bb50e61fccaa519274bd6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for ULPS.  <a href="#ga3ad7fcdb85bb50e61fccaa519274bd6f">More...</a><br/></td></tr>
<tr class="separator:ga3ad7fcdb85bb50e61fccaa519274bd6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8444ef3ccc6b6a472a6393fd5326027e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga8444ef3ccc6b6a472a6393fd5326027e">XMIPI_TX_PHY_CLSTATUS_REG_MODE_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga8444ef3ccc6b6a472a6393fd5326027e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Mode bits.  <a href="#ga8444ef3ccc6b6a472a6393fd5326027e">More...</a><br/></td></tr>
<tr class="separator:ga8444ef3ccc6b6a472a6393fd5326027e"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Bitmasks and offsets of XMIPI_TX_PHY_DLxSTATUS_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp21f4d33e495a4c45bf8274f1e59a2f4c"></a>This register contains the data lanes status </p>
</td></tr>
<tr class="memitem:ga37f17efe16bf0d8be132b6e0619a341e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga37f17efe16bf0d8be132b6e0619a341e">XMIPI_TX_PHY_DLXSTATUS_REG_PACKETCOUNT_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:ga37f17efe16bf0d8be132b6e0619a341e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet Count.  <a href="#ga37f17efe16bf0d8be132b6e0619a341e">More...</a><br/></td></tr>
<tr class="separator:ga37f17efe16bf0d8be132b6e0619a341e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac00ba9ecef3361a5bb9fcf0e20a9c6e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gac00ba9ecef3361a5bb9fcf0e20a9c6e6">XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_STATUS_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:gac00ba9ecef3361a5bb9fcf0e20a9c6e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calib status.  <a href="#gac00ba9ecef3361a5bb9fcf0e20a9c6e6">More...</a><br/></td></tr>
<tr class="separator:gac00ba9ecef3361a5bb9fcf0e20a9c6e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabcf51a2a9b4602aa06828c55b7fef9d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gabcf51a2a9b4602aa06828c55b7fef9d4">XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gabcf51a2a9b4602aa06828c55b7fef9d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Calib complete.  <a href="#gabcf51a2a9b4602aa06828c55b7fef9d4">More...</a><br/></td></tr>
<tr class="separator:gabcf51a2a9b4602aa06828c55b7fef9d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f65a8dea651af7702362ae7ef30e191"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga6f65a8dea651af7702362ae7ef30e191">XMIPI_TX_PHY_DLXSTATUS_REG_STOP_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga6f65a8dea651af7702362ae7ef30e191"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop State on data lane.  <a href="#ga6f65a8dea651af7702362ae7ef30e191">More...</a><br/></td></tr>
<tr class="separator:ga6f65a8dea651af7702362ae7ef30e191"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad128be776c9344fcec21c7ad7579a2c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gad128be776c9344fcec21c7ad7579a2c1">XMIPI_TX_PHY_DLXSTATUS_REG_ESCABRT_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gad128be776c9344fcec21c7ad7579a2c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set on Data Lane Esc timeout occurs.  <a href="#gad128be776c9344fcec21c7ad7579a2c1">More...</a><br/></td></tr>
<tr class="separator:gad128be776c9344fcec21c7ad7579a2c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga54d606cb5490a7e1dd6f2f123c028833"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga54d606cb5490a7e1dd6f2f123c028833">XMIPI_TX_PHY_DLXSTATUS_REG_HSABRT_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga54d606cb5490a7e1dd6f2f123c028833"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set on Data Lane HS timeout.  <a href="#ga54d606cb5490a7e1dd6f2f123c028833">More...</a><br/></td></tr>
<tr class="separator:ga54d606cb5490a7e1dd6f2f123c028833"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga65aea4fb42069d3515c6667c03b90804"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga65aea4fb42069d3515c6667c03b90804">XMIPI_TX_PHY_DLXSTATUS_REG_INITDONE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga65aea4fb42069d3515c6667c03b90804"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set after initialization.  <a href="#ga65aea4fb42069d3515c6667c03b90804">More...</a><br/></td></tr>
<tr class="separator:ga65aea4fb42069d3515c6667c03b90804"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9a2034abf3cea4fd0d702dc9d364ff0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaf9a2034abf3cea4fd0d702dc9d364ff0">XMIPI_TX_PHY_DLXSTATUS_REG_ULPS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaf9a2034abf3cea4fd0d702dc9d364ff0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set when MIPI_TX_PHY in ULPS mode.  <a href="#gaf9a2034abf3cea4fd0d702dc9d364ff0">More...</a><br/></td></tr>
<tr class="separator:gaf9a2034abf3cea4fd0d702dc9d364ff0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5bf3d01103d08acc8bbb1cf2cb80ef4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gab5bf3d01103d08acc8bbb1cf2cb80ef4">XMIPI_TX_PHY_DLXSTATUS_REG_MODE_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:gab5bf3d01103d08acc8bbb1cf2cb80ef4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Mode (Esc, Low, High) of Data Lane.  <a href="#gab5bf3d01103d08acc8bbb1cf2cb80ef4">More...</a><br/></td></tr>
<tr class="separator:gab5bf3d01103d08acc8bbb1cf2cb80ef4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga35fe51d4fe33d10564b2676597896aa5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga35fe51d4fe33d10564b2676597896aa5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XMIPI_TX_PHY_DLXSTATUS_ALLMASK</b></td></tr>
<tr class="separator:ga35fe51d4fe33d10564b2676597896aa5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabfa6f4bbcae507932db411474983c466"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gabfa6f4bbcae507932db411474983c466">XMIPI_TX_PHY_DLXSTATUS_REG_PACKCOUNT_OFFSET</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gabfa6f4bbcae507932db411474983c466"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset packet count.  <a href="#gabfa6f4bbcae507932db411474983c466">More...</a><br/></td></tr>
<tr class="separator:gabfa6f4bbcae507932db411474983c466"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb2c29072f2f4470428afb2b2fb66e28"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gaeb2c29072f2f4470428afb2b2fb66e28">XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_STATUS_OFFSET</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gaeb2c29072f2f4470428afb2b2fb66e28"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset calib status.  <a href="#gaeb2c29072f2f4470428afb2b2fb66e28">More...</a><br/></td></tr>
<tr class="separator:gaeb2c29072f2f4470428afb2b2fb66e28"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga28466e4ed8a8e07b00371f6e6062189b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga28466e4ed8a8e07b00371f6e6062189b">XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_OFFSET</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:ga28466e4ed8a8e07b00371f6e6062189b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset Calib complete.  <a href="#ga28466e4ed8a8e07b00371f6e6062189b">More...</a><br/></td></tr>
<tr class="separator:ga28466e4ed8a8e07b00371f6e6062189b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4802b5075a9ba293b4c0f3ba76d46905"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga4802b5075a9ba293b4c0f3ba76d46905">XMIPI_TX_PHY_DLXSTATUS_REG_STOP_OFFSET</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga4802b5075a9ba293b4c0f3ba76d46905"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Stop State.  <a href="#ga4802b5075a9ba293b4c0f3ba76d46905">More...</a><br/></td></tr>
<tr class="separator:ga4802b5075a9ba293b4c0f3ba76d46905"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga78e9d7fe89467eb850509947b1695619"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga78e9d7fe89467eb850509947b1695619">XMIPI_TX_PHY_DLXSTATUS_REG_ESCABRT_OFFSET</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:ga78e9d7fe89467eb850509947b1695619"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Escape Abort.  <a href="#ga78e9d7fe89467eb850509947b1695619">More...</a><br/></td></tr>
<tr class="separator:ga78e9d7fe89467eb850509947b1695619"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacfe5c375a23a599452314f778b88cf94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gacfe5c375a23a599452314f778b88cf94">XMIPI_TX_PHY_DLXSTATUS_REG_HSABRT_OFFSET</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:gacfe5c375a23a599452314f778b88cf94"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for High Speed Abort.  <a href="#gacfe5c375a23a599452314f778b88cf94">More...</a><br/></td></tr>
<tr class="separator:gacfe5c375a23a599452314f778b88cf94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace1a0b197742830a78fb50293fdc557e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gace1a0b197742830a78fb50293fdc557e">XMIPI_TX_PHY_DLXSTATUS_REG_INITDONE_OFFSET</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gace1a0b197742830a78fb50293fdc557e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Initialization done.  <a href="#gace1a0b197742830a78fb50293fdc557e">More...</a><br/></td></tr>
<tr class="separator:gace1a0b197742830a78fb50293fdc557e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c0a16f8b0feca7fe3f8cc6f54b1af2d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga5c0a16f8b0feca7fe3f8cc6f54b1af2d">XMIPI_TX_PHY_DLXSTATUS_REG_ULPS_OFFSET</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga5c0a16f8b0feca7fe3f8cc6f54b1af2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for ULPS.  <a href="#ga5c0a16f8b0feca7fe3f8cc6f54b1af2d">More...</a><br/></td></tr>
<tr class="separator:ga5c0a16f8b0feca7fe3f8cc6f54b1af2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d4bf96f1ff599cf39682ae6f7733369"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga4d4bf96f1ff599cf39682ae6f7733369">XMIPI_TX_PHY_DLXSTATUS_REG_MODE_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga4d4bf96f1ff599cf39682ae6f7733369"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Modes.  <a href="#ga4d4bf96f1ff599cf39682ae6f7733369">More...</a><br/></td></tr>
<tr class="separator:ga4d4bf96f1ff599cf39682ae6f7733369"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Bitmask and offset of XMIPI_TX_PHY_HSSETTLE_REG_OFFSET register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp10d37df7325d9bc2d3ee9ae75f43f115"></a>This register is used to program the HS SETTLE register.</p>
<p>Default value is 135 + 10UI. </p>
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<tr class="memitem:gadd2ac13ad244c63767708f50754e91eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#gadd2ac13ad244c63767708f50754e91eb">XMIPI_TX_PHY_HSSETTLE_REG_TIMEOUT_MASK</a>&#160;&#160;&#160;0x1FF</td></tr>
<tr class="memdesc:gadd2ac13ad244c63767708f50754e91eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS_SETTLE value.  <a href="#gadd2ac13ad244c63767708f50754e91eb">More...</a><br/></td></tr>
<tr class="separator:gadd2ac13ad244c63767708f50754e91eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga288b6d3f90fa63aa3d6ea45d19e12746"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mipi__tx__phy.html#ga288b6d3f90fa63aa3d6ea45d19e12746">XMIPI_TX_PHY_HSSETTLE_REG_TIMEOUT_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga288b6d3f90fa63aa3d6ea45d19e12746"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for HS_SETTLE.  <a href="#ga288b6d3f90fa63aa3d6ea45d19e12746">More...</a><br/></td></tr>
<tr class="separator:ga288b6d3f90fa63aa3d6ea45d19e12746"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ga89763534a7c4bbbb64696d34d35df25c"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CLSTATUS_REG_ERRCTRL_MASK&#160;&#160;&#160;0x00000020</td>
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<p>Clock lane control error. </p>
<p>Only for RX </p>

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</div>
<a class="anchor" id="ga17528c58e673adc82f62fbeab06b22b8"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CLSTATUS_REG_ERRCTRL_OFFSET&#160;&#160;&#160;5</td>
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<p>Bit offset for Control Error on Clock. </p>

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</div>
<a class="anchor" id="ga2b1c1cac54af04e31c36599ed6e8062a"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CLSTATUS_REG_INITDONE_MASK&#160;&#160;&#160;0x00000008</td>
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<p>Initialization done bit. </p>

</div>
</div>
<a class="anchor" id="gace4f962db90a3d55720867e7e0eb81cc"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CLSTATUS_REG_INITDONE_OFFSET&#160;&#160;&#160;3</td>
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<p>Bit offset for Initialization Done. </p>

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<a class="anchor" id="gaec485fecc0d01a6803f437395cc66f5b"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CLSTATUS_REG_MODE_MASK&#160;&#160;&#160;0x00000003</td>
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<p>Low, High, Esc mode. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#gaa1ad1388f716aaff8073d17268341007">XMipi_Tx_Phy_GetClkLaneMode()</a>.</p>

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</div>
<a class="anchor" id="ga8444ef3ccc6b6a472a6393fd5326027e"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CLSTATUS_REG_MODE_OFFSET&#160;&#160;&#160;0</td>
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<p>Bit offset for Mode bits. </p>

</div>
</div>
<a class="anchor" id="gaee3555d2cc9dc91c2f13f39f246af4ac"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CLSTATUS_REG_OFFSET&#160;&#160;&#160;0x00000018</td>
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<p>Clk lane PHY error Status Register. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga96324c0e81aae087966b15ed5478830e">XMipi_Tx_Phy_GetClkLaneStatus()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ga9bcfcbfc2bc59101377b603ee65b87ae"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CLSTATUS_REG_STOPSTATE_MASK&#160;&#160;&#160;0x00000010</td>
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<p>Clock lane stop state. </p>

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<a class="anchor" id="ga9f13683048291c23c8a62cb99de4159a"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CLSTATUS_REG_STOPSTATE_OFFSET&#160;&#160;&#160;4</td>
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<p>Bit offset for Stop State on Clock. </p>

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<a class="anchor" id="ga6aece57daaccf4f982fddf764b15a868"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CLSTATUS_REG_ULPS_MASK&#160;&#160;&#160;0x00000004</td>
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<p>Set in ULPS mode. </p>

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<a class="anchor" id="ga3ad7fcdb85bb50e61fccaa519274bd6f"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CLSTATUS_REG_ULPS_OFFSET&#160;&#160;&#160;2</td>
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<p>Bit offset for ULPS. </p>

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</div>
<a class="anchor" id="gabbf8c59ccf6c1abcef8dd1c7cb06473c"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CTRL_REG_OFFSET&#160;&#160;&#160;0x00000000</td>
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<p>Control Register. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga1ea4f73d453197f5d121170ae4db05c9">XMipi_Tx_Phy_Activate()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga60dbd7f0c7cc211f6ed1e97c8c1dd8c0">XMipi_Tx_Phy_Reset()</a>.</p>

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<a class="anchor" id="gae8340e846c67ddfc75a11bbd4ac5269d"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CTRL_REG_PHYEN_MASK&#160;&#160;&#160;0x00000002</td>
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<p>Enable/Disable controller. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga1ea4f73d453197f5d121170ae4db05c9">XMipi_Tx_Phy_Activate()</a>.</p>

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<a class="anchor" id="gaba9c09bed36f1c618981e53063651f68"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CTRL_REG_PHYEN_OFFSET&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for PHY Enable. </p>

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<a class="anchor" id="gaff7758fee41117064aa8d27b5ee69de7"></a>
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          <td class="memname">#define XMIPI_TX_PHY_CTRL_REG_SOFTRESET_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
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<p>Soft Reset. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga60dbd7f0c7cc211f6ed1e97c8c1dd8c0">XMipi_Tx_Phy_Reset()</a>.</p>

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</div>
<a class="anchor" id="gaab53fbae94c162e2810f2e8bc4d19130"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_CTRL_REG_SOFTRESET_OFFSET&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Soft Reset. </p>

</div>
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<a class="anchor" id="ga77c981eb784b931ddee9637d03dfafa6"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DL0STATUS_REG_OFFSET&#160;&#160;&#160;0x0000001C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data lane 0 PHY error Status Register. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0e324919c833e8a3044f5807a4e88a6f">XMipi_Tx_Phy_ClearDataLane()</a>, <a class="el" href="group__mipi__tx__phy.html#ga30186d35cb2a9a6e8c176a2e12b8fc3c">XMipi_Tx_Phy_GetDataLaneStatus()</a>, <a class="el" href="group__mipi__tx__phy.html#gaf9e0be75428b66fe7d9f22b8b223e66b">XMipi_Tx_Phy_GetDLCalibStatus()</a>, <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>, and <a class="el" href="group__mipi__tx__phy.html#gae03f90199460c27b38aca1a9eecd973c">XMipi_Tx_Phy_GetPacketCount()</a>.</p>

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<a class="anchor" id="ga16d4d03a4897453d51733d12036c3b02"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DL1STATUS_REG_OFFSET&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data lane 1 PHY error Status Register. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="gaf23b1a894f2241c14d64c555f90a7447"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DL2STATUS_REG_OFFSET&#160;&#160;&#160;0x00000024</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data lane 2 PHY error Status Register. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga79aad6bfa8e6ae4383887cb10eeb7ef8"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DL3STATUS_REG_OFFSET&#160;&#160;&#160;0x00000028</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data lane 3 PHY error Status Register. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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</div>
<a class="anchor" id="gabcf51a2a9b4602aa06828c55b7fef9d4"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK&#160;&#160;&#160;0x00000080</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Calib complete. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#gaf9e0be75428b66fe7d9f22b8b223e66b">XMipi_Tx_Phy_GetDLCalibStatus()</a>.</p>

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<a class="anchor" id="ga28466e4ed8a8e07b00371f6e6062189b"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_OFFSET&#160;&#160;&#160;7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset Calib complete. </p>

</div>
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<a class="anchor" id="gac00ba9ecef3361a5bb9fcf0e20a9c6e6"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_STATUS_MASK&#160;&#160;&#160;0x00000100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Calib status. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#gaf9e0be75428b66fe7d9f22b8b223e66b">XMipi_Tx_Phy_GetDLCalibStatus()</a>.</p>

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</div>
<a class="anchor" id="gaeb2c29072f2f4470428afb2b2fb66e28"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_STATUS_OFFSET&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset calib status. </p>

</div>
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<a class="anchor" id="gad128be776c9344fcec21c7ad7579a2c1"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_ESCABRT_MASK&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Set on Data Lane Esc timeout occurs. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0e324919c833e8a3044f5807a4e88a6f">XMipi_Tx_Phy_ClearDataLane()</a>.</p>

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<a class="anchor" id="ga78e9d7fe89467eb850509947b1695619"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_ESCABRT_OFFSET&#160;&#160;&#160;5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Escape Abort. </p>

</div>
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<a class="anchor" id="ga54d606cb5490a7e1dd6f2f123c028833"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_HSABRT_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
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<p>Set on Data Lane HS timeout. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0e324919c833e8a3044f5807a4e88a6f">XMipi_Tx_Phy_ClearDataLane()</a>.</p>

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<a class="anchor" id="gacfe5c375a23a599452314f778b88cf94"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_HSABRT_OFFSET&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for High Speed Abort. </p>

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<a class="anchor" id="ga65aea4fb42069d3515c6667c03b90804"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_INITDONE_MASK&#160;&#160;&#160;0x00000008</td>
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      </table>
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<p>Set after initialization. </p>

</div>
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<a class="anchor" id="gace1a0b197742830a78fb50293fdc557e"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_INITDONE_OFFSET&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Initialization done. </p>

</div>
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<a class="anchor" id="gab5bf3d01103d08acc8bbb1cf2cb80ef4"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_MODE_MASK&#160;&#160;&#160;0x00000003</td>
        </tr>
      </table>
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<p>Control Mode (Esc, Low, High) of Data Lane. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga921e82addba856d2b57c15ac8ace54eb">XMipi_Tx_Phy_GetDataLaneMode()</a>.</p>

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</div>
<a class="anchor" id="ga4d4bf96f1ff599cf39682ae6f7733369"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_MODE_OFFSET&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Modes. </p>

</div>
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<a class="anchor" id="gabfa6f4bbcae507932db411474983c466"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_PACKCOUNT_OFFSET&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset packet count. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#gae03f90199460c27b38aca1a9eecd973c">XMipi_Tx_Phy_GetPacketCount()</a>.</p>

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</div>
<a class="anchor" id="ga37f17efe16bf0d8be132b6e0619a341e"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_PACKETCOUNT_MASK&#160;&#160;&#160;0xFFFF0000</td>
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      </table>
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<p>Packet Count. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#gae03f90199460c27b38aca1a9eecd973c">XMipi_Tx_Phy_GetPacketCount()</a>.</p>

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<a class="anchor" id="ga6f65a8dea651af7702362ae7ef30e191"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_STOP_MASK&#160;&#160;&#160;0x00000040</td>
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<p>Stop State on data lane. </p>

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<a class="anchor" id="ga4802b5075a9ba293b4c0f3ba76d46905"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_STOP_OFFSET&#160;&#160;&#160;6</td>
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<p>Bit offset for Stop State. </p>

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<a class="anchor" id="gaf9a2034abf3cea4fd0d702dc9d364ff0"></a>
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_ULPS_MASK&#160;&#160;&#160;0x00000004</td>
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<p>Set when MIPI_TX_PHY in ULPS mode. </p>

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<a class="anchor" id="ga5c0a16f8b0feca7fe3f8cc6f54b1af2d"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_DLXSTATUS_REG_ULPS_OFFSET&#160;&#160;&#160;2</td>
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      </table>
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<p>Bit offset for ULPS. </p>

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<a class="anchor" id="ga9e75abdbbf8a802143da1077354cf90c"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_ESCAPE_MODE&#160;&#160;&#160;2</td>
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<p>Lane in Escape Mode. </p>

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<a class="anchor" id="ga3dd41b223fba7f1f0c099f9444944b19"></a>
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          <td class="memname">#define XMIPI_TX_PHY_ESCTIMEOUT_REG_OFFSET&#160;&#160;&#160;0x00000014</td>
        </tr>
      </table>
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<p>Goto Stop state on timeout timer Register. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga3b3542421ec553cab65cbdb1145b146a"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_ESCTIMEOUT_REG_VAL_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
        </tr>
      </table>
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<p>Escape Timout Value. </p>

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</div>
<a class="anchor" id="gaf1b47a9cfeecf567a00b6ae5e3b1ae55"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_ESCTIMEOUT_REG_VAL_OFFSET&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit offset for Escape Timeout. </p>

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<a class="anchor" id="gafab4174d7ffe2e9118d2f388914f26e3"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_H_</td>
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</div><div class="memdoc">

<p>Prevent circular inclusions by using protection macros. </p>

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<a class="anchor" id="ga2792b35f19f06efb8b6adb0c3e7c0f7f"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_HANDLE_CLKLANE&#160;&#160;&#160;4</td>
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<p>Handle for Clock Lane. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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</div>
<a class="anchor" id="ga8ca0ab2cf3f6b368c2454200b780ef03"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_HANDLE_DLANE0&#160;&#160;&#160;5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Handle for Data Lane 0. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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</div>
<a class="anchor" id="ga8fa083c47f619744ed568fcc76d1d4aa"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_HANDLE_DLANE1&#160;&#160;&#160;6</td>
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<p>Handle for Data Lane 1. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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</div>
<a class="anchor" id="ga7ebd16502a0c0ee0d4b0cb99c7b4af94"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_HANDLE_DLANE2&#160;&#160;&#160;7</td>
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<p>Handle for Data Lane 2. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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</div>
<a class="anchor" id="ga61d3f8f2a197488723c7f18de5fa4452"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_HANDLE_DLANE3&#160;&#160;&#160;8</td>
        </tr>
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<p>Handle for Data Lane 3. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="gaf48cd41ce4fbada5662e23018611c003"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_HANDLE_ESCTIMEOUT&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Handle for Escape Timeout. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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<a class="anchor" id="ga45d5dd17088900a16fec2d4ec72055fb"></a>
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<div class="memproto">
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          <td class="memname">#define XMIPI_TX_PHY_HANDLE_HSTIMEOUT&#160;&#160;&#160;2</td>
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<p>Handle for HS Timeout. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure()</a>, <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga4a6f46a83ce56b8538bd115feb1e652f">XMipi_Tx_Phy_SelfTest()</a>.</p>

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</div>
<a class="anchor" id="ga794d4197e4f32ea40dc8010b2ae0185c"></a>
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          <td class="memname">#define XMIPI_TX_PHY_HANDLE_INIT_TIMER&#160;&#160;&#160;1</td>
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<p>Handle for Initialization Timer. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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          <td class="memname">#define XMIPI_TX_PHY_HANDLE_MAX&#160;&#160;&#160;9</td>
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<p>Upper Bound for XMIPI_TX_PHY_HANDLE. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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          <td class="memname">#define XMIPI_TX_PHY_HANDLE_MIN&#160;&#160;&#160;0</td>
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<p>Lower Bound for XMIPI_TX_PHY_HANDLE. </p>

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          <td class="memname">#define XMIPI_TX_PHY_HIGH_POWER_MODE&#160;&#160;&#160;1</td>
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<p>Lane in High Power Mode. </p>

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          <td class="memname">#define XMIPI_TX_PHY_HSSETTLE_REG_TIMEOUT_MASK&#160;&#160;&#160;0x1FF</td>
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<p>HS_SETTLE value. </p>

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          <td class="memname">#define XMIPI_TX_PHY_HSSETTLE_REG_TIMEOUT_OFFSET&#160;&#160;&#160;0</td>
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<p>Bit offset for HS_SETTLE. </p>

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          <td class="memname">#define XMIPI_TX_PHY_HSTIMEOUT_REG_OFFSET&#160;&#160;&#160;0x00000010</td>
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<p>Watchdog timeout in HS mode Register. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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<p>HS_TX_TIMEOUT Received. </p>

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          <td class="memname">#define XMIPI_TX_PHY_HSTIMEOUT_REG_TIMEOUT_OFFSET&#160;&#160;&#160;0</td>
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<p>Bit offset for Timeout. </p>

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          <td class="memname">#define XMIPI_TX_PHY_HW_H_</td>
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<p>Prevent circular inclusions by using protection macros. </p>

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          <td class="memname">#define XMIPI_TX_PHY_INIT_REG_VAL_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
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<p>Init Timer value in ns. </p>

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          <td class="memname">#define XMIPI_TX_PHY_INIT_REG_VAL_OFFSET&#160;&#160;&#160;0</td>
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<p>Bit offset for Init Timer. </p>

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          <td class="memname">#define XMIPI_TX_PHY_INIT_TIMER_REG_OFFSET&#160;&#160;&#160;0x00000008</td>
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<p>Initialization Timer Register. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga0edf3de0af6e081ab9ec6ba03bcb029d">XMipi_Tx_Phy_Configure()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>.</p>

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          <td class="memname">#define XMIPI_TX_PHY_LOW_POWER_MODE&#160;&#160;&#160;0</td>
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<p>Lane in Low Power Mode. </p>

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          <td class="memname">#define XMIPI_TX_PHY_MAX_LANES_V10&#160;&#160;&#160;4</td>
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<p>V1.0 supports 4 Lanes. </p>

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          <td class="memname">#define XMIPI_TX_PHY_MODE_MAX&#160;&#160;&#160;2</td>
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<p>Upper Limit for mode. </p>

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          <td class="memname">#define XMIPI_TX_PHY_MODE_MIN&#160;&#160;&#160;0</td>
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<p>Lower limit for Mode. </p>

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          <td class="memname">#define XMIPI_TX_PHY_PROG_SEQ_CTRL_OFFSET&#160;&#160;&#160;0x00000038</td>
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<p>Prog Seq Control Register. </p>

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          <td class="memname">#define XMIPI_TX_PHY_PROG_SEQ_DATA0_OFFSET&#160;&#160;&#160;0x0000003C</td>
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<p>Prog Seq Data Register 0. </p>

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          <td class="memname">#define XMIPI_TX_PHY_PROG_SEQ_DATA1_OFFSET&#160;&#160;&#160;0x00000040</td>
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<p>Prog Seq Data Register 1. </p>

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          <td class="memname">#define XMIPI_TX_PHY_PROG_SEQ_EN_MASK&#160;&#160;&#160;0x1</td>
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<p>Enable/Disable Prog Seq. </p>

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          <td class="memname">#define XMIPI_TX_PHY_VERSION_REG_OFFSET&#160;&#160;&#160;0x00000004</td>
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<p>Core Version Register. </p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga35253890ab16b4233209c20890d18ecb">XMipi_Tx_Phy_GetVersionReg()</a>.</p>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">void XMipi_Tx_Phy_Activate </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Flag</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function is used to enable or disable the Mipi_Tx_Phy core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">Flag</td><td>denoting whether to enable or disable the Mipi_Tx_Phy core</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy___config.html#a4673423aeb644c8cf11fe30fbaf19b04">XMipi_Tx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__tx__phy.html#gabbf8c59ccf6c1abcef8dd1c7cb06473c">XMIPI_TX_PHY_CTRL_REG_OFFSET</a>, and <a class="el" href="group__mipi__tx__phy.html#gae8340e846c67ddfc75a11bbd4ac5269d">XMIPI_TX_PHY_CTRL_REG_PHYEN_MASK</a>.</p>

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          <td class="memname">u32 XMipi_Tx_Phy_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy___config.html">XMipi_Tx_Phy_Config</a> *&#160;</td>
          <td class="paramname"><em>CfgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Initialize the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance provided by the caller based on the given Config structure. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">CfgPtr</td><td>is the device configuration structure containing information about a specific Mipi_Tx_Phy instance. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS Initialization was successful.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy___config.html#a4673423aeb644c8cf11fe30fbaf19b04">XMipi_Tx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, and <a class="el" href="struct_x_mipi___tx___phy.html#a56f91293f1bd1129e782b457a99812ae">XMipi_Tx_Phy::IsReady</a>.</p>

<p>Referenced by <a class="el" href="xmipi__tx__phy__example__selftest_8c.html#a9893e377f68273dd05a2d26d47a99a23">Mipi_Tx_PhySelfTestExample()</a>.</p>

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          <td class="memname">void XMipi_Tx_Phy_ClearDataLane </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DataLane</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Mask</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
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<p>This is used to clear the Abort Error (Escape or High Speed) bits in the Data Lane 0 through 3. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">DataLane</td><td>represents which Data Lane to act upon </td></tr>
    <tr><td class="paramname">Mask</td><td>contains information about which bits to reset</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy___config.html#a4673423aeb644c8cf11fe30fbaf19b04">XMipi_Tx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__tx__phy.html#ga77c981eb784b931ddee9637d03dfafa6">XMIPI_TX_PHY_DL0STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__tx__phy.html#gad128be776c9344fcec21c7ad7579a2c1">XMIPI_TX_PHY_DLXSTATUS_REG_ESCABRT_MASK</a>, and <a class="el" href="group__mipi__tx__phy.html#ga54d606cb5490a7e1dd6f2f123c028833">XMIPI_TX_PHY_DLXSTATUS_REG_HSABRT_MASK</a>.</p>

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          <td class="memname">u32 XMipi_Tx_Phy_Configure </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Handle</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Value</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Configure the registers of the Mipi_Tx_Phy instance. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">Handle</td><td>to one of the registers to be configured </td></tr>
    <tr><td class="paramname">Value</td><td>to be set for the particular Handle of the Mipi_Tx_Phy instance</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS on successful register update.</li>
<li>XST_FAILURE If incorrect handle was passed</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>There is a limit on the minimum and maximum values of the HS Timeout register. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__tx__phy.html#ga3dd41b223fba7f1f0c099f9444944b19">XMIPI_TX_PHY_ESCTIMEOUT_REG_OFFSET</a>, <a class="el" href="group__mipi__tx__phy.html#ga2792b35f19f06efb8b6adb0c3e7c0f7f">XMIPI_TX_PHY_HANDLE_CLKLANE</a>, <a class="el" href="group__mipi__tx__phy.html#ga8ca0ab2cf3f6b368c2454200b780ef03">XMIPI_TX_PHY_HANDLE_DLANE0</a>, <a class="el" href="group__mipi__tx__phy.html#ga8fa083c47f619744ed568fcc76d1d4aa">XMIPI_TX_PHY_HANDLE_DLANE1</a>, <a class="el" href="group__mipi__tx__phy.html#ga7ebd16502a0c0ee0d4b0cb99c7b4af94">XMIPI_TX_PHY_HANDLE_DLANE2</a>, <a class="el" href="group__mipi__tx__phy.html#ga61d3f8f2a197488723c7f18de5fa4452">XMIPI_TX_PHY_HANDLE_DLANE3</a>, <a class="el" href="group__mipi__tx__phy.html#gaf48cd41ce4fbada5662e23018611c003">XMIPI_TX_PHY_HANDLE_ESCTIMEOUT</a>, <a class="el" href="group__mipi__tx__phy.html#ga45d5dd17088900a16fec2d4ec72055fb">XMIPI_TX_PHY_HANDLE_HSTIMEOUT</a>, <a class="el" href="group__mipi__tx__phy.html#ga794d4197e4f32ea40dc8010b2ae0185c">XMIPI_TX_PHY_HANDLE_INIT_TIMER</a>, <a class="el" href="group__mipi__tx__phy.html#ga4dd60256bbac14dbc8b023397aa7a4ef">XMIPI_TX_PHY_HANDLE_MAX</a>, <a class="el" href="group__mipi__tx__phy.html#ga38135baf5eb6b624dacae2760a87f276">XMIPI_TX_PHY_HSTIMEOUT_REG_OFFSET</a>, and <a class="el" href="group__mipi__tx__phy.html#ga06d4f400a133fadb577204eb236d8b60">XMIPI_TX_PHY_INIT_TIMER_REG_OFFSET</a>.</p>

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          <td class="memname">u32 XMipi_Tx_Phy_GetClkLaneMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This is used to get specific Lane mode information about Clock Lane. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Bitmask containing mode in which the Clock Lane in Mipi_Tx_Phy is in.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#ae278036709d322cc21888b24463a01f3">XMipi_Tx_Phy_Config::IsDphy</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__tx__phy.html#gaec485fecc0d01a6803f437395cc66f5b">XMIPI_TX_PHY_CLSTATUS_REG_MODE_MASK</a>, and <a class="el" href="group__mipi__tx__phy.html#ga96324c0e81aae087966b15ed5478830e">XMipi_Tx_Phy_GetClkLaneStatus()</a>.</p>

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          <td class="memname">u32 XMipi_Tx_Phy_GetClkLaneStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This is used to get information about Clock Lane status. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Bitmask containing which of the events have occured along with the mode of the Clock Lane in DPhy</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy___config.html#a4673423aeb644c8cf11fe30fbaf19b04">XMipi_Tx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#ae278036709d322cc21888b24463a01f3">XMipi_Tx_Phy_Config::IsDphy</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>, and <a class="el" href="group__mipi__tx__phy.html#gaee3555d2cc9dc91c2f13f39f246af4ac">XMIPI_TX_PHY_CLSTATUS_REG_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#gaa1ad1388f716aaff8073d17268341007">XMipi_Tx_Phy_GetClkLaneMode()</a>.</p>

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          <td class="memname">u32 XMipi_Tx_Phy_GetDataLaneMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DataLane</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This is used to get specfic Lane mode information about a Data Lane. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">DataLane</td><td>for which the mode info is requested.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Bitmask containing mode in which the Data Lane in Mipi_Tx_Phy is in.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__tx__phy.html#gab5bf3d01103d08acc8bbb1cf2cb80ef4">XMIPI_TX_PHY_DLXSTATUS_REG_MODE_MASK</a>, and <a class="el" href="group__mipi__tx__phy.html#ga30186d35cb2a9a6e8c176a2e12b8fc3c">XMipi_Tx_Phy_GetDataLaneStatus()</a>.</p>

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          <td class="memname">u32 XMipi_Tx_Phy_GetDataLaneStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DataLane</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This is used to get information about a Data Lane status. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">DataLane</td><td>for which the status is sought for.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Bitmask containing which of the events have occured along with the mode of the Data Lane in DPhy</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy___config.html#a4673423aeb644c8cf11fe30fbaf19b04">XMipi_Tx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>, and <a class="el" href="group__mipi__tx__phy.html#ga77c981eb784b931ddee9637d03dfafa6">XMIPI_TX_PHY_DL0STATUS_REG_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga921e82addba856d2b57c15ac8ace54eb">XMipi_Tx_Phy_GetDataLaneMode()</a>.</p>

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          <td class="memname">u8 XMipi_Tx_Phy_GetDLCalibStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DataLane</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This is used to get Data Lane Calibration status. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">DataLane</td><td>for which the calib status is sought for.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>XST_SUCCESS - Calibration Complete, Calibration packet received XST_NO_DATA - Calibration Complete, Calibration packet is not received XST_FAILURE - Calibration failed</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy___config.html#a4673423aeb644c8cf11fe30fbaf19b04">XMipi_Tx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__tx__phy.html#ga77c981eb784b931ddee9637d03dfafa6">XMIPI_TX_PHY_DL0STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__tx__phy.html#gabcf51a2a9b4602aa06828c55b7fef9d4">XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_COMPLETE_MASK</a>, and <a class="el" href="group__mipi__tx__phy.html#gac00ba9ecef3361a5bb9fcf0e20a9c6e6">XMIPI_TX_PHY_DLXSTATUS_REG_CALIB_STATUS_MASK</a>.</p>

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          <td class="memname">u32 XMipi_Tx_Phy_GetInfo </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Handle</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Get information stored in the Mipi_Tx_Phy instance based on the handle passed. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">Handle</td><td>to one of the registers to be configured</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The value stored in the corresponding register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#ae278036709d322cc21888b24463a01f3">XMipi_Tx_Phy_Config::IsDphy</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a442de8892fdd7791c701e3bee870b38a">XMipi_Tx_Phy_Config::MaxLanesPresent</a>, <a class="el" href="group__mipi__tx__phy.html#gaee3555d2cc9dc91c2f13f39f246af4ac">XMIPI_TX_PHY_CLSTATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__tx__phy.html#ga77c981eb784b931ddee9637d03dfafa6">XMIPI_TX_PHY_DL0STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__tx__phy.html#ga16d4d03a4897453d51733d12036c3b02">XMIPI_TX_PHY_DL1STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__tx__phy.html#gaf23b1a894f2241c14d64c555f90a7447">XMIPI_TX_PHY_DL2STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__tx__phy.html#ga79aad6bfa8e6ae4383887cb10eeb7ef8">XMIPI_TX_PHY_DL3STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__tx__phy.html#ga3dd41b223fba7f1f0c099f9444944b19">XMIPI_TX_PHY_ESCTIMEOUT_REG_OFFSET</a>, <a class="el" href="group__mipi__tx__phy.html#ga2792b35f19f06efb8b6adb0c3e7c0f7f">XMIPI_TX_PHY_HANDLE_CLKLANE</a>, <a class="el" href="group__mipi__tx__phy.html#ga8ca0ab2cf3f6b368c2454200b780ef03">XMIPI_TX_PHY_HANDLE_DLANE0</a>, <a class="el" href="group__mipi__tx__phy.html#ga8fa083c47f619744ed568fcc76d1d4aa">XMIPI_TX_PHY_HANDLE_DLANE1</a>, <a class="el" href="group__mipi__tx__phy.html#ga7ebd16502a0c0ee0d4b0cb99c7b4af94">XMIPI_TX_PHY_HANDLE_DLANE2</a>, <a class="el" href="group__mipi__tx__phy.html#ga61d3f8f2a197488723c7f18de5fa4452">XMIPI_TX_PHY_HANDLE_DLANE3</a>, <a class="el" href="group__mipi__tx__phy.html#gaf48cd41ce4fbada5662e23018611c003">XMIPI_TX_PHY_HANDLE_ESCTIMEOUT</a>, <a class="el" href="group__mipi__tx__phy.html#ga45d5dd17088900a16fec2d4ec72055fb">XMIPI_TX_PHY_HANDLE_HSTIMEOUT</a>, <a class="el" href="group__mipi__tx__phy.html#ga794d4197e4f32ea40dc8010b2ae0185c">XMIPI_TX_PHY_HANDLE_INIT_TIMER</a>, <a class="el" href="group__mipi__tx__phy.html#ga4dd60256bbac14dbc8b023397aa7a4ef">XMIPI_TX_PHY_HANDLE_MAX</a>, <a class="el" href="group__mipi__tx__phy.html#ga38135baf5eb6b624dacae2760a87f276">XMIPI_TX_PHY_HSTIMEOUT_REG_OFFSET</a>, and <a class="el" href="group__mipi__tx__phy.html#ga06d4f400a133fadb577204eb236d8b60">XMIPI_TX_PHY_INIT_TIMER_REG_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="group__mipi__tx__phy.html#ga4a6f46a83ce56b8538bd115feb1e652f">XMipi_Tx_Phy_SelfTest()</a>.</p>

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          <td class="memname">u16 XMipi_Tx_Phy_GetPacketCount </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>DataLane</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This is used to get count of packets received on each lane. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on. </td></tr>
    <tr><td class="paramname">DataLane</td><td>for which the mode info is requested.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Bitmask containing mode in which the Data Lane in Mipi_Tx_Phy is in.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy___config.html#a4673423aeb644c8cf11fe30fbaf19b04">XMipi_Tx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__tx__phy.html#ga77c981eb784b931ddee9637d03dfafa6">XMIPI_TX_PHY_DL0STATUS_REG_OFFSET</a>, <a class="el" href="group__mipi__tx__phy.html#gabfa6f4bbcae507932db411474983c466">XMIPI_TX_PHY_DLXSTATUS_REG_PACKCOUNT_OFFSET</a>, and <a class="el" href="group__mipi__tx__phy.html#ga37f17efe16bf0d8be132b6e0619a341e">XMIPI_TX_PHY_DLXSTATUS_REG_PACKETCOUNT_MASK</a>.</p>

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          <td class="memname">u8 XMipi_Tx_Phy_GetRegIntfcPresent </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>Get if register interface is present from the config structure for specified Mipi_Tx_Phy instance. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>1 if register interface is present</li>
<li>0 if register interface is absent</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, and <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>.</p>

<p>Referenced by <a class="el" href="xmipi__tx__phy__example__selftest_8c.html#a9893e377f68273dd05a2d26d47a99a23">Mipi_Tx_PhySelfTestExample()</a>.</p>

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          <td class="memname">u32 XMipi_Tx_Phy_GetVersionReg </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This is used to get Mipi_Tx_Phy Version. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns major and minor Version number of this Mipi_Tx_Phy IP</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy___config.html#a4673423aeb644c8cf11fe30fbaf19b04">XMipi_Tx_Phy_Config::BaseAddr</a>, <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>, and <a class="el" href="group__mipi__tx__phy.html#ga6e16ded337e70f28b3ba7c3c791f736a">XMIPI_TX_PHY_VERSION_REG_OFFSET</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_mipi___tx___phy___config.html">XMipi_Tx_Phy_Config</a> * XMipi_Tx_Phy_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BaseAddress</em></td><td>)</td>
          <td></td>
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<p>Look up the hardware configuration for a device instance. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the BaseAddress of the device to lookup for</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The reference to the configuration record in the configuration table (in xmipi_tx_phy_g.c) corresponding to the BaseAddr or if not found,a NULL pointer is returned.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p>Referenced by <a class="el" href="xmipi__tx__phy__example__selftest_8c.html#a9893e377f68273dd05a2d26d47a99a23">Mipi_Tx_PhySelfTestExample()</a>.</p>

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          <td class="memname">void XMipi_Tx_Phy_Reset </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This is used to do a soft reset of the Mipi_Tx_Phy IP instance. </p>
<p>The reset takes approx 20 core clock cycles to become effective.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance to operate on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy.html#a56f91293f1bd1129e782b457a99812ae">XMipi_Tx_Phy::IsReady</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a0db9d0089b4a24b665a8e5f1c32e4f98">XMipi_Tx_Phy_Config::IsRegisterPresent</a>, <a class="el" href="group__mipi__tx__phy.html#gabbf8c59ccf6c1abcef8dd1c7cb06473c">XMIPI_TX_PHY_CTRL_REG_OFFSET</a>, and <a class="el" href="group__mipi__tx__phy.html#gaff7758fee41117064aa8d27b5ee69de7">XMIPI_TX_PHY_CTRL_REG_SOFTRESET_MASK</a>.</p>

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          <td class="memname">u32 XMipi_Tx_Phy_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_mipi___tx___phy.html">XMipi_Tx_Phy</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>Runs a self-test on the driver/device. </p>
<p>This test checks if HS Timeout value present in register matches the one from the generated file.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_mipi___tx___phy.html" title="The Xmipi_tx_phy Controller driver instance data. ">XMipi_Tx_Phy</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if self-test was successful</li>
</ul>
</dd></dl>
<ul>
<li>XST_FAILURE if the read value was not equal to _g.c file</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_mipi___tx___phy.html#a537c46a9f925d363e47dcaa75cd6fab1">XMipi_Tx_Phy::Config</a>, <a class="el" href="struct_x_mipi___tx___phy___config.html#a2377c4cd19231e1c33268348bcc1ecfe">XMipi_Tx_Phy_Config::HSTimeOut</a>, <a class="el" href="group__mipi__tx__phy.html#ga3647fa8d8f8ed5ef13a940a00959ce90">XMipi_Tx_Phy_GetInfo()</a>, and <a class="el" href="group__mipi__tx__phy.html#ga45d5dd17088900a16fec2d4ec72055fb">XMIPI_TX_PHY_HANDLE_HSTIMEOUT</a>.</p>

<p>Referenced by <a class="el" href="xmipi__tx__phy__example__selftest_8c.html#a9893e377f68273dd05a2d26d47a99a23">Mipi_Tx_PhySelfTestExample()</a>.</p>

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